An improved low-power clock-gating pulse-triggered JK flip-flop

摘要：

In this paper, an improved clock-gating pulsetriggered JK Flip-flop (CG-PT-JKFF) for low-power requirements is presented. It is based on clockgating technique, and power consumption is reduced because redundant internal switching activities are eliminated. When probability of activities of the flip-flop is 25％, the improved flip-flop can save up to 41％ of the Power.

关键词： JK flip-flop low-power clock-gating CMOS pulse-triggered

作者: Zhao Xianghong Guo Jiankang Song Guanghui

作者单位: Ningbo Institute of Technology, Zhejiang University Ningbo, China

会议类型: 国际会议

会议名称: 2010 International Conference on Information,Networking and Automation(2010 IEEE信息网络与自动化国际会议 ICINA 2010)

会议地点: 昆明

会议语种:英文

页码: 489-491

在线出版日期: 2010-10-17（万方平台首次上网日期，不代表论文的发表时间）