Configurable FFT Processor

摘要：

In this paper, a configurable FFT processor is presented which can be configured as 8192 point, 4096 point, 2048 point and 1024 point FFT processor. The processor is based on mixed radix algorithm and single-path delay feedback(SDF) architecture is adopted. The configurable architecture is achieved by connecting or bypassing specific processing elements. To improve processor performance, a dynamic scaling approach is adopted and internal data is formatted as self-defined floating point, and the arithmetic for the self-defined floating point is simple. The experiment results show that the approach can achieve high and constant SNR. The processor is implemented on FPGA.

关键词： FFT configurable architecture dynamic scaling

作者: He Jing Ma Lanjuan Xu Xinyu

作者单位: Information Engineering School Communication University of China Beijing 100024, China

会议类型: 国际会议

会议名称: 2010 The IET 3rd International Conference on Wireless,Mobile & Multimedia Networks(第三届IET无线移动及多媒体网络国际会议 ICWMMN 2010)

会议地点: 北京

会议语种:英文

页码: 246-249

在线出版日期: 2010-09-26（万方平台首次上网日期，不代表论文的发表时间）