VLSI Implementation of Sub-pixel Interpolator for AVS Encoder
Interpolation is the main bottleneck in AVS real-time high definition video encoder for its high memory bandwidth and large calculation complexity caused by the new coding features of variable block size and 4tap filter. In this paper, a high performance VLSI architecture of interpolation supporting AVS Baseline@L4 is presented. Vertical redundant data reuse, horizontal redundant data reuse and sub-pixel data reuse schemes are presented to reduce memory bandwidth and processing cycle. The separated 1-D interpolation filters are used to improve throughput and hardware utilization. The proposed design is implemented on FPGA with operating frequency of 150MHz and can support 1080p (1920xl080)/30fps AVS real-time encoder. It is a useful intellectual property design for real-time high definition video application.
AVS interpolation data reuse separated 1-D architecture
Chen Guanghua Wang Anqi Hu Dengji Ma Shiwei Zeng Weimin
School of Mechatronics Engineering and Automation, Shanghai Key Laboratory of Power Station Automati Key Laboratory of Advanced Display and System Applications, Ministry of Education & Microelectronic
国际会议
无锡
英文
351-359
2010-09-17（万方平台首次上网日期，不代表论文的发表时间）