High-throughout Hardware Architecture of MQ Arithmetic Coder

摘要：

A novel byte-out architecture in MQ arithmetic coder is proposed and the new MQ-coder hardware archirecture which use the novel byte-out architecture is presented, in which it can encode two CX-D pairs per cycle. The coder is describled with Verilog HDL at RTL. Synthesis, fitter, assembler and timing analyzer are conducted with Quartus..9.0. The results of timing analyzer show that the architecture can efficiently improve the throughput and clock frequency, the throughput can achieve 117.12 MCxD·s-1 and the clock frequency can achieve 58.56 MHz.

关键词： JPEG2000 MQ arithmetic coder throughput hardware archirecture

作者: PENG Zhou ZHAO Bao-jun

作者单位: Radar Research Laboratory, Beijing Institute of Technology, Beijing, China

会议类型: 国际会议

会议名称: 2010 IEEE 10th International Conference on Signal Processing(第十届信号处理国际会议 ICSP 2010)

会议地点: 北京

会议语种:英文

页码: 430-433

在线出版日期: 2010-08-24（万方平台首次上网日期，不代表论文的发表时间）