Minimal Instruction Set AES Processor using Harvard Architecture

摘要：

This paper presents an FPGA implementation of Advance Encryption Standard (AES), using Minimal Instruction Set Computer (MISC) with Harvard Architecture. With simple logic components and a minimum set of fundamental instructions, the MISC using Harvard Architecture enables the AES encryption in severely constraint hardware environment, with lesser execution clock cycles. The MISC architecture was verified using the Handel-C hardware description language and implemented on a Xilinx Spartan3 FPGA. The implementation uses two separate block RAMs and occupied only 1 ％ of the total available chip area.

关键词： Minimal Instruction Set Computer Computer Security AES

作者: J.H.Kong L.-M.Ang K.P.Seng

作者单位: Department of Electrical and Electronic Engineering University Of Nottingham Malaysia Campus Jalan Broga, Semenyih, 43500 Selangor, Malaysia

会议类型: 国际会议

会议名称: 2010 3rd IEEE International Conference on Computer Science and Information Technology(第三届IEEE计算机科学与信息技术国际会议 ICCSIT 2010)

会议地点: 成都

会议语种:英文

页码: 65-69

在线出版日期: 2010-07-07（万方平台首次上网日期，不代表论文的发表时间）