Comparison of Two Data Hazard Handling Schemes for Asynchronous Pipelined Processors

摘要：

Since asynchronous logic adopts a distributed control scheme, the traditional methods for handling hazards in synchronous processors cannot be directly applied to asynchronous processors. Recently, the data hazard detection table (DHDT) scheme has been regarded as an effective method for handling data hazards in asynchronous processors. In this paper, two asynchronous data hazard handling schemes, the DHDT scheme and the proposed destination register chain (DRC) scheme, are compared in terms of performance and hardware complexity. In order to evaluate these two data hazard handling schemes, we have used the Balsa asynchronous synthesis system to implement two asynchronous pipelined processors, AsynRISC-DHDT and AsynRISC-DRC, which employ DHDT and DRC, respectively-, to deal with data hazards. Experimental results show that AsynRISC-DRC can achieve a 13％ reduction in hardware area cost and a performance gain of 22.1％ compared with AsynRISCDHDT.

关键词： asynchronous logic pipelined processor data hazard data hazard detection table

作者: Meng-Chou Chang Da-Sen Shiau

作者单位: Department of Electronic Engineering National Changhua University of Education Changhua, Taiwan, ROC

会议类型: 国际会议

会议名称: 2010 3rd IEEE International Conference on Computer Science and Information Technology(第三届IEEE计算机科学与信息技术国际会议 ICCSIT 2010)

会议地点: 成都

会议语种:英文

页码: 36-40

在线出版日期: 2010-07-07（万方平台首次上网日期，不代表论文的发表时间）