System Verifacation based on VMM and SOPC
This paper presents a new type of a more complete system verification method, which combines a highlevel verification methodology based on verification methodology manual (VMM) techniques for functional simulation and system-on-a-programmable-chip (SOPC) techniques for board-level verification, effectively improve the adequacy and reliability of verification and validation efficiency.This paper gives a scalable hierarchical verification platform used systemverilog,which achieved the constraint-random stimulus generation, assertion monitoring, automatic real-time comparison for outputs and coverage statistics. Additionally, this paper describes the development of the test environment and the entire physical verification platform.
verifacation System verifacation VMM SOPC
Jinbin Hu Xiaoguang Li
School of Electronics and Information Engineering Beijing Jiaotong University Beijing,China
国际会议
成都
英文
41-43
2010-07-07（万方平台首次上网日期，不代表论文的发表时间）