Conflict Graph Based Hardware Transactional Memory
This paper proposes a novel transactional memory design: conflict graph based hardware transactional memory. It allows two conflicting transactions both to commit if they do not violate the condition of serializability. Simulation results show that conflict graph based hardware transactional memory outperforms the state-of-art transactional memory system.
transactional memory conflict detection serializability conflict graph
Kun Zeng
National University of Defense Technology National Laboratory for Parallel and Distributed Processing,School of Computer National University of Defense Technology ChangSha,Hunan,China
国际会议
成都
英文
496-501
2010-07-07(万方平台首次上网日期,不代表论文的发表时间)