Low Power Cache Architecture with Security Mechanism
Embedded cryptographic devices not only suffer from traditional physical side channel attacks, but also undergo software cache-based side channel attacks recently. The attacks can easily get the users confidential data via information leakage in caches, and dont require any special instruments. Among existing countermeasures, software solutions can defend the attacks perfectly while leading to significant performance degradation. Hardware solutions are very effective in reducing performance overhead while their structures are complex. This paper presents a novel easily implemented cache architecture which has an added small cache and adopts certain operation mechanism. Compared with traditional cache architecture, it has reduction in miss rate ranging between 20％ and 50％, and has about 8.5％ of reduction in power consumption, and is secure at the same time. This paper presents both theoretical analysis and experimental results. In our experiments, the Mi Bench suite is used to evaluate the cache performance of miss rate and energy consumption, and the security of cache is also analyzed. It also supplies the result of Synopsys Design Compiler of the RTL cache code under the 0.18μm CMOS technology.
cache computer architecture low power security
Chang Li Fei Qiao Huazhong Yang
Dept.of Electronic Engineering, Tsinghua National Laboratory for Information Science and Technology Tsinghua University, Beijing, China
国际会议
上海
英文
573-577
2010-06-22（万方平台首次上网日期，不代表论文的发表时间）