会议专题

Comparing Simulations and Graphical Representations of Complexities of Benchmark and Large-Variable Circuits

In this work, we analyzes the relationship between randomly generated Boolean function complexity and the number of nodes in benchmark circuits using the Binary Decision Diagrams (BDD). We generated BDDs for several ISCAS benchmark circuits and derived the area complexity measure in terms of number of nodes. We demonstrate that the benchmarks and randomly generated Boolean functions behave similarly in terms of area complexity. The experiments were extended to a large number of variables to verify the complexity behavior. It was confirmed that the rise of the complexity graph is only important to calculate the circuit complexities.

Binary Decision diagram Benchmark circuits Area Complexity

Prasad P.W.C. Azam Beg Ashutosh Kumar Singh

Charles Sturt University,Sydney Study Centre,NSW, Australia College of Information Technology UAE University, Al-Ain,United Arab Emirates Department of Electrical and Computer Engineering Curtain University of Technology Sarawak Campus, M

国际会议

2010 2nd International Conference on Education Technology and Computer(第二届IEEE教育技术与计算机国际会议 ICETC 2010)

上海

英文

134-138

2010-06-22(万方平台首次上网日期,不代表论文的发表时间)