RS encoder design based on FPGA

摘要：

A time-domain RS (Reed-Solomon) encoder was studied in this paper.Firstly analyzed coding theory of RS codes under the finite field,and focuses on the implementations of constant coefficients parallel multiplier under regular basis.On this basis,designed the encoder of RS (255,223) symmetrical structure in the Quartus7.0 build environment using the symmetry of polynomial coefficients,and use Matlab to prepare RS encoder debug and procedures verification,finally,obtained simulation results with the ModelSim5.8.The results show that the encoder is in good condition,and speed and occupancy characteristics of the hardware resources are limited compared with the existing type design.

关键词： FPGA Reed-Solomon codes encoder

作者: Chang Xiaojun Guo Jun Li Zhihui

作者单位: College of Information Science and Technology Northwest University Xian,China School of Economics and Management Beijing University of Posts and Telecommunications Beijing,China

会议类型: 国际会议

会议名称: The 2nd IEEE International Conference on Advanced Computer Control(第二届先进计算机控制国际会议 ICACC 2010)

会议地点: 沈阳

会议语种:英文

页码: 419-421

在线出版日期: 2010-03-27（万方平台首次上网日期，不代表论文的发表时间）