MDAC Design for 1.5-bit Pipeline Stage of High-Speed High-Resolution ADC
This paper presents a design of residue amplification circuit (MDAC) used in the first 1.5-bit pipeline stage of an ADC,and the MDAC should meet requirements of a 100MS/s 14-bit pipeline ADC with 1.8V supply voltage.In order to obtain the corresponding performance,the circuits such as operational amplifier and bootstrap circuit are designed which could realize the objective of high-speed and highresolution.The gain-boost structure is used in the amplifier to obtain the specified resolution,and an optimization between speed and power dissipation should be carefully conducted as a high speed requires a large slew rate or trans-conductance which is proportional to power dissipation.The design is implemented in the 0.18μm CMOS process with 9.6mW power consumption and the simulation results in Spectre illustrate that,the designed operational amplifier could reach the fixed objective and the residue signal of MDAC could set up completely in the specified time 3ns.
pipeline MDAC operational amplifier bootstrap circuit set up
Zhang Guo-min Yin Yong-sheng Deng Hong-hui
Institute of VLSI Design Hefei University of Technology Hefei,China
国际会议
The 2nd IEEE International Conference on Advanced Computer Control(第二届先进计算机控制国际会议 ICACC 2010)
沈阳
英文
456-459
2010-03-27（万方平台首次上网日期，不代表论文的发表时间）