A Design of HDB3 CODEC Based on FPGA

摘要：

The basic principles and structure of HDB3 was briefly introduced in this paper, and the shortcomings of the existing HDB3 encoder and decoder was analyzed. Then a new design of HDB3 encoder and decoder based on FPGA was proposed, and the hardware design circuit and software simulation were introduced. The simulation was achieved through the VERILOG-HDL in EP2C35F672C8 chip of Cyclonell series in the development environment of Quartus II 7.2. The results show that the design meets the requirements of HDB3 encoder and decoder, which has a simple hardware circuit and flexible software, and runs fast,and can be used in practical communication systems.

关键词： FPGA HDB3 Encoder and Decoder

作者: Zhang Chang-sen Xu Qi

作者单位: College of Computer Science & Technology Henan Polytechnic University JiaoZuo, China College of Computer Science & Technology Henan Polytechnic University JiaoZuo,China

会议类型: 国际会议

会议名称: The 2nd IEEE International Conference on Advanced Computer Control(第二届先进计算机控制国际会议 ICACC 2010)

会议地点: 沈阳

会议语种:英文

页码: 75-78

在线出版日期: 2010-03-27（万方平台首次上网日期，不代表论文的发表时间）