Topology Synthesis of Application-specific Network-on-Chip Using Two-level Genetic Algorithm
As the number of intellectual property (IP) cores integrated on a single chip increases, the on-chip communication becomes the major performance bottleneck of high-end System-on-chip. NoCs have emerged as the most prominent solution to on-chip communication problems. The objective of topology synthesis is to minimize the power consumption and router resources while satisfying bandwidth constraints. In this paper, we present a two-level geneticalgorithm based technique to synthesize application-specific NoC topology. Comparing to an existing three-level GA, experiments show that our technique saves 1.14% energy while saving great runtimes of 97.88%. Our technique generates approximate optimal topology less than one minute.
system-on-chip (SoC) network-on-chip (NoC) Application-Specific NoC genetic algorithms topology synthesis
Guoming Lai Xiaola Lin Guoming Lai
School of Information Science and Technology Sun Yat-sen University Guangzhou, 510006, China School of Information Science and TechnologySun Yat-sen UniversityGuangzhou, 510006, China Department of Math and Information TechnologyHanshan Normal UniversityChaozhou, 521041, China
国际会议
哈尔滨
英文
485-489
2011-01-18(万方平台首次上网日期,不代表论文的发表时间)