A Study in Functional Verification of ASIP

摘要：

Functional verification has become the bottleneck in designing of Application Specific Instruction-Set Processor (ASIP). The paper presents a functional verification methodology with great efficiency in designing of ASIP based on hardware structure and instruction-set, which is composed of the component-level verification, the instruction-level verification and the FPGA-based prototype system verification. Experimental results show the methodology has distinctly increased the coverage in the component-level verification and the instruction-level verification comparing with the traditional methodology.

关键词： Application Specific Instruction-Set Processor (ASIP) component-level verification instruction-level verification prototype system verification coverage

作者: Jianzhou Xu Jinhai Su Zibin Dai Wei Li

作者单位: Zhengzhou Information Science and Technology InstituteZhengzhou, China Zhengzhou Information Science and Technology Institute Zhengzhou, China

会议类型: 国际会议

会议名称: 2011 International Conference on Information System and Computational Intelligence(2011 IEEE信息系统与计算智能国际会议 ICISCI 2011)

会议地点: 哈尔滨

会议语种:英文

页码: 343-346

在线出版日期: 2011-01-18（万方平台首次上网日期，不代表论文的发表时间）