A low power PFD and dual mode CP with small current mismatch for PLL application

摘要：

Abstract — A high speed Phase-Frequency Detector (PFD) and Charge Pump (CP) are implemented using 0.13μm CMOS process with 1.2 V supply. The PFD is implemented with TSPC (True Single-Phase Clock) and positive edge triggered D flipflop. Its polarity can be changed by setting the port. The dead zone problem is solved using an additional reset time. A single charge pump is implemented with two compensators. Dual mode CP design makes the charge pump much more flexible in applications. The current mismatch for the two modes is below 4.9％ within the voltage range of from 0.2 to 1.0 V.

关键词： PLL PFD CP

作者: Cao Yu Minsu Kim Hyungchul Kim Youngoo Yang

作者单位: MCS Lab, school of information and communication, SungKyunKwan UniversitySuwon, South KOREA MCS Lab, school of information and communication, SungKyunKwan University Suwon, South KOREA

会议类型: 国际会议

会议名称: 2011 International Conference on Information System and Computational Intelligence(2011 IEEE信息系统与计算智能国际会议 ICISCI 2011)

会议地点: 哈尔滨

会议语种:英文

页码: 161-164

在线出版日期: 2011-01-18（万方平台首次上网日期，不代表论文的发表时间）