Digitally Assisted Backend Correction Pipeline ADC Verilog-A Modeling

摘要：

In this paper, a 12 bits pipeline ADC (analog to digital converter) based on digitally assisted backend correction is described and behaviorally modeled in Verilog-A language. The Verilog-A model is simulated with Cadence Spectre simulator. In the traditional use of pipeline ADC, the for-end sample and hold amplifier occupies the most power consumption. To decreases the system power consumption, open-loop amplifier is used in the first residual amplify circuit between first and second stage sub-ADC. To correct the nonlinear error introduced by the open-loop amplifier, backend digitally correction is applied.

关键词： component

作者: GONG Yuehong LUO Min MA jianguo

作者单位: Micro electronics and solid-state electronics department HIT haerbin, China Micro electronics and solid-state electronics departmentHIThaerbin, China Electronics and information engineeringTianjin universityTianjin, China

会议类型: 国际会议

会议名称: 2011 International Conference on Information System and Computational Intelligence(2011 IEEE信息系统与计算智能国际会议 ICISCI 2011)

会议地点: 哈尔滨

会议语种:英文

页码: 485-489

在线出版日期: 2011-01-18（万方平台首次上网日期，不代表论文的发表时间）