Design of the Digital Baseband of RFID tag based on EPC C1G2

摘要：

This paper presents the design of the digital baseband of RFID tag based on EPC Class 1 Generation2, which is comprehensive passive RFID protocol today. Several low power techniques are employed to reduce the power consumption of the baseband: Clock Frequency Reduction, Clock Gating and Operand Isolation, and discrete chaotic logistic map and register-reuse techniques are applied to the design of the architecture of baseband. The baseband circuit is implemented in TSMC 0.18 μm CMOS process. The chip area is 351 li m X 353 u m excluding test pads. The power consumption is 15.2 u W under 1.8V supply voltage.

关键词： RFID EPC C1G2 tag digital baseband

作者: Wen Qiao Quanyuan Feng

作者单位: Institute of Microelectronics, Southwest Jiaotong University, Chengdu, China

会议类型: 国际会议

会议名称: 2011 International Conference on Information and Industrial Electronics(2011年信息与工业电子国际会议 ICIIE 2011)

会议地点: 成都

会议语种:英文

页码: 462-465

在线出版日期: 2011-01-14（万方平台首次上网日期，不代表论文的发表时间）