Research on Parallelization Accelerating SPH Algorithm with Multi-core CPUs
This paper presents design of parallelization accelerating SPH algorithm with Multi-core CPUs, and the implementation of the experimental system. By contrast, speed of the parallelization program is 7.4 times faster than serial program with Xeon 8 cores CPU. Some problems which refer to parallelization accelerating SPH algorithm are noticed in the field of computer architecture. The issues about how to improve cache-hit rate and reduce memory transfer, especially for the process of neighborhood searching are discussed. Additionally, an improved method for neighborhood data structure is also given in this paper.
fluid simulation SPH thread multi-core
Guo Jie Long Xiang Gao Xiaopeng
State Key Laboratory of Virtual Reality Technology and System, School of Computer Science and Engine Institute of Computer Architectures, School of Computer Science and Engineering, Beihang University,
国际会议
2011 International Conference on Information and Industrial Electronics(2011年信息与工业电子国际会议 ICIIE 2011)
成都
英文
812-815
2011-01-14（万方平台首次上网日期，不代表论文的发表时间）