Cache Management By Conflict Prediction

摘要：

In this paper a cache scheme named Conflict Prediction Cache(CP cache) is presented. Its architecture contains a direct-mapped cache and a small fully-associative cache, and a conflict prediction table(CPT) which dynamically decides the allocation of fetched blocks from next memory hierarchy. SPEC95 Simulation results show that the performance of CP cache is always better than the traditional direct-mapped cache with twice the size of CP cache. For example, with the same block size of 32 bytes, the average improvement of miss rate of (8+ 1 )KB CP cache with 8-entry CPT is about 19％ over the traditional 16KB direct-mapped cache. By comparison with other similar architectures such as NTS cache and PCS cache, CP cache not only requires less hardware tradeoff and simpler control but also improves hit rate and bus traffic.

关键词： conflict prediction miss rate cache performance

作者: Li Xiaoming Fu Fangfa Xiao Liyi Bao Dongxing

作者单位: Microelectronics Center Harbin Institute of Technology Harbin, China School of Electronic Engineering Heilongjiang University Harbin, China

会议类型: 国际会议

会议名称: 2011 International Conference on Information and Industrial Electronics(2011年信息与工业电子国际会议 ICIIE 2011)

会议地点: 成都

会议语种:英文

页码: 834-837

在线出版日期: 2011-01-14（万方平台首次上网日期，不代表论文的发表时间）