A Low Cost Approach For Auxiliary Monitoring In FPGA-Based Fault Tolerant Computer

摘要：

Single computer usually unable to diagnose itself. Therefore, fault monitoring module or multiple computers are often used in fault tolerant computer system. This paper presents an FPGA-based method of fault detection by creating a redundant soft-core CPU to do identical process for FPGA-based fault tolerant computer system, without increasing any hardware to achieve the internal FPGA non-fatal failure selfdiscovery, such as SEU (Single Event Upset). System judges whether an FPGA is running correctly by comparing results from Auxiliary Monitoring redundant soft-core CPU and the original soft-core CPU, though cannot find the failure where is but can isolate or mask the failure, and this approach gets a lower cost for traditional fault tolerant computer system. It can increase the reliability of overall system with 1.74 percent (from 0.982378 to 0.999512) under the module reliability supposition in this paper for TMR (Triple Modular Redundant) system.

关键词： Fault detection FPGA Architecture PC/104

作者: Yinghong Zhang Jihong Zhu Jinxia An

作者单位: Department of Computer Science and Technology Tsinghua University Beijing, China

会议类型: 国际会议

会议名称: 2010 International Conference on Future Information Technology(2010年未来信息技术国际会议 ICFIT 2010)

会议地点: 长沙

会议语种:英文

页码: 42-46

在线出版日期: 2010-12-14（万方平台首次上网日期，不代表论文的发表时间）