New Method of SOC Clock Design Based on Hierarchical Mode

摘要：

The new problems of traditional clock design in hierarchical mode were analyzed in this paper and a new method of clock design was proposed. A phase_sync signal was used as a bridge of top-level and sub-design in this method. It effectively prevents the damage to the internal timing of subdesign caused by top-level timing closure. The application of this method avoids reset design of clock divider circuit and reduces the difficulty of physical design.

关键词： component: flatten design hierarchy design clock skew1 phase sync synchronizer(1)

作者: WANG DANDAN

作者单位: School of electrical and information engineering Wuhan Institute of Technology Wuhan 430070, China

会议类型: 国际会议

会议名称: 2010 International Conference on Signal and Information Processing(2010年IEEE信号与信息处理国际会议 ICSIP2010)

会议地点: 长沙

会议语种:英文

页码: 365-367

在线出版日期: 2010-12-14（万方平台首次上网日期，不代表论文的发表时间）