A VLSI Architecture for Real-time Signal FFT Based on Pipelined Processing Element

摘要：

In this paper, a VLSI architecture for real-time. signal FFT based on pipelined processing element (PE) is proposed. The proposed architecture suits to FFT/I FFT and supports input/output simultaneously. In the system a 2~MN point FFT can be computed by 2~M point rowwise FFT followed by 2~N point column-wise 2-D FFT. By this way long length FFT is divided continuously until it could be conquered by some short length processing elements (PE). The proposed pipelined PE architectures are based on short length FFT algorithms used in WFTA, so multiplier number in PEs is minimal. A 1024-point complex FFT is implemented in XC2VP30-7 FPGA board based on the VLSI architecture. Result shows that latency between input and output is about 3300 clock cycles, and the computation time for real-time signal FFT is minimal compare to recent research. The proposed architecture also has flexible configuration for different point FFT.

关键词： Fast Fourier transform (FFT) 2-D Fast Fourier transform Real-time signal processing

作者: Wang Xu Zhang Yan Wang Jiannan

作者单位: Shenzhen Graduate School, Harbin Institute of Technology Shenzhen, China

会议类型: 国际会议

会议名称: 2010 International Conference on Signal and Information Processing(2010年IEEE信号与信息处理国际会议 ICSIP2010)

会议地点: 长沙

会议语种:英文

页码: 633-637

在线出版日期: 2010-12-14（万方平台首次上网日期，不代表论文的发表时间）