Hardware Accelerator Design for Change Detection in Smart Camera
Smart Cameras are important components in Human Computer Interaction. In any remote surveillance scenario, smart cameras have to take intelligent decisions to select frames of significant changes to minimize communication and processing overhead. Among many of the algorithms for change detection, one based on clustering based scheme was proposed for smart camera systems. However, such an algorithm could achieve low frame rate far from realtime requirements on a general purpose processors (like PowerPC) available on FPGAs. This paper proposes the hardware accelerator capable of detecting real time changes in a scene, which uses clustering based change detection scheme. The system is designed and simulated using VHDL and implemented on Xilinx XUP Virtex-IIPro FPGA board. Resulted frame rate is 30 frames per second for QVGA resolution in gray scale.
Change Detection Smart Camera FPGA Implementation
Sanjay Singh Member IEEE Srinivasa Murali Dunga Ravi Saini AS Mandal Chandra Shekhar Santanu Chaudhury Anil Vohra
Central Electronics Engineering Research Institute (CEERI) / Council of Scientific and Industrial Re Electrical Engineering Department Indian Institute of Technology Delhi, India Electronic Science Department. Kurukshetra University, Kurukshetra Haryana, India
国际会议
2010 International Conference on Signal and Information Processing(2010年IEEE信号与信息处理国际会议 ICSIP2010)
长沙
英文
749-751
2010-12-14（万方平台首次上网日期，不代表论文的发表时间）