Framework for HW/SW Partitioning and Scheduling on MPSoCs
Hardware/software (HW/SW) partitioning and scheduling are the most significant parts in codesign systems, especially in multiprocessor systemon-chip (MPSoC). It has been shown that both problems, HW/SW partitioning and HW/SW scheduling, are NP-hard. In this paper, we propose a framework for the HW/SW partitioning and scheduling. The proposed approach initially searches for typical subgraphs in the original task graph and then reduces them to the supper nodes, in order to minimize the communication overheads. After that, the proposed algorithm schedules the tasks of the reduced task graph to the target MPSoC, according to the assigned priority to the tasks. Then, we contribute an efficient HW/SW partitioning technique to minimize the overall execution time, based on the iteratively constructing critical path and moving the tasks with the high computing cost to hardware. Simulation results show that the proposed framework in this paper is better than the existing one.
hardware/software co-design partitioning scheduling MPSoC embedded system
Honglei Han Liu Wenju Wu Jigang Li Hui
School of Computer Science and Software Tianjin Polytechnic University, Tianjin, China, 300160
国际会议
2010 International Conference on Computer and Information Application(2010年计算机与信息应用国际会议 ICCIA 2010)
天津
英文
182-185
2010-12-03(万方平台首次上网日期,不代表论文的发表时间)