会议专题

Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level

In recent technology nodes, reliability is considered a part of the standard design flow at all levels of embedded system design. While techniques that use only low-level models at gate- and register transferlevel offer high accuracy, they are too inefficient to consider the overall application of the embedded system. Multi-level models with high abstraction are essential to efficiently evaluate the impact of physical defects on the system. This paper provides a methodology that leverages state-of-the-art techniques for efficient fault simulation of structural faults together with transaction-level modeling. This way it is possible to accurately evaluate the impact of the faults on the entire hardware/software system. A case study of a system consisting of hardware and software for image compression and data encryption is presented and the method is compared to a standard gate/RT mixed-level approach.

Fault simulation multi-level transaction-level modeling

Michael A. Kochte Christian G. Zoellin Rafal Baranowski Nadereh Hatami Stefano Di Carlo Michael E. Imhof Hans-Joachim Wunderlich

University of Stuttgart Institute of Computer Architecture and Computer Engineering Pfaffenwaldring University of Stuttgart Institute of Computer Architecture and Computer Engineering Pfaffenwaldring Paolo Prinetto Politecnico di Torino Dipartimento di Automatica e Informatica Corso Duca degli Abruz

国际会议

2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

上海

英文

3-8

2010-12-01(万方平台首次上网日期,不代表论文的发表时间)