Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment
In this paper we are revisiting the issue of sequential circuit test generation, and use a selective random pattern test generation method implemented in an HDL environment. The method uses a statistical expectation graph and states of the sequential circuit for selecting the appropriate test vectors to achieve better fault coverage and a more compact test set. To further reduce the size of the generated test set, a static compaction method, which is also implemented in an HDL environment, is used after the test generation process. The experimental results show that selecting good test patterns among random test patterns, not only can be implemented dynamically in an HDL design environment, but also results in a better fault coverage and shorter test pattern length in comparison with some traditional deterministic methods. In addition, it will be shown that static test set compaction methods can considerably reduce the test length of test patterns for sequential designs obtained by our proposed method.
sequential circuit random test generation PLI shortest sequence expectation graph compaction
M. H. Haghbayan S. Karamati F. Javaheri Z. Navabi
Electrical and Computer Engineering Department School of Engineering Colleges- Campus＃2- University of Tehran, 1450 North Amirabad, 14395-515 Tehran, Iran
国际会议
2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)
上海
英文
53-56
2010-12-01（万方平台首次上网日期，不代表论文的发表时间）