Variation-Aware Fault Modeling
To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defectoriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defectfree case. This allows distinguishing the effects of process variations on the cell delay from defectinduced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level information beyond the HDB. The generation of the HDB is demonstrated for primitive cells in 45nm technology.
Defect-oriented testing parameter variations delay analogue fault simulation histograms
Fabian Hopsch Bernd Becker Sybille Hellebrand Ilia Polian Bernd Straube Hans-Joachim
Fraunhofer IIS/EAS Dresden, Germany University of Freiburg Germany University of Paderborn Germany University of Passau Germany Wolfgang Vermeiren Fraunhofer IIS/EAS Dresden, Germany Wunderlich University of Stuttgart Germany
国际会议
2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)
上海
英文
87-93
2010-12-01(万方平台首次上网日期,不代表论文的发表时间)