A Low Cost Built-in Self-Test Circuit for High-Speed Source Synchronous Memory Interfaces
A built-in self-test (BIST) for testing high speed source-synchronous memory interfaces has been designed using 0.18-μm TSMC process. To overcome limitations of the resolution and the accuracy in low-cost automated test equipment (ATE), a cycle-by-cycle controllable embedded pattern generator in the proposed BIST scheme is presented to specify performance-related I/O parameters. Using this method, the I/O parameters affected by the internal and the external mismatches are investigated by measuring the relative timing differences between the data lines and the strobe signal. The measurement results are monitored with low frequency output by using dividers and the embedded pattern generator. The advantage of this low cost approach is that it does not require ATE to access high frequency signals for testing. Monte Carlo simulations are performed to verify the circuit operations, and the experimental results show the measurement of I/O parameters for 1.6Gbps memory devices.
Built-in Self-Test Source Synchronous Interfaces DDR High Speed Memory I/Os ATE
Hyunjin Kim Jacob A. Abraham
Computer Engineering Research Center The University of Texas at Austin, University Station C8800, TX 78712
国际会议
2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)
上海
英文
123-128
2010-12-01（万方平台首次上网日期，不代表论文的发表时间）