A Complete Logic BIST Technology with No Storage Requirement
Mixed-mode BIST enhances test efficiency of digital circuits by combining the advantages of both pseudorandom and deterministic patterns. In order to apply the deterministic patterns, most traditional methods need to store some test data in external testers or on-chip memory. In this paper we present a novel mixed-mode BIST technique by which all deterministic patterns can be generated on chip in real time and thus requiring no storage device. By appropriately connecting some internal nets of the circuit under test to the inputs of the circuit, together with a set of pseudo-random patterns, this BIST scheme can reach full fault coverage in a very short time. Experimental results show that all irredundant stuck-at faults in each of the ISCAS85 benchmarks can be detected in less than WOO test cycles with no storage space required.
Wei-Cheng Lien Kuen-Jong Lee
Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan 70101
国际会议
2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)
上海
英文
129-134
2010-12-01（万方平台首次上网日期，不代表论文的发表时间）