Test Data Reduction for BIST-aided Scan Test Using Compatible Flip-flops and Shifting Inverter Code

摘要：

In this paper, a method for reducing test data volume of BIST-aided scan test (BAST) is proposed. In our BAST method, scan chains are ordered using compatible flip-flops to reduce the conflicting bits between ATPG pattern and random pattern obtained by LFSR. The inverter block in BIST-aided scan architecture is modified for shifting inverter code such that the random pattern produced by LFSR has less conflicting bits with ATPG patterns when providing the test pattern to the scan chains. The experimental results show the method can reduce the test data volume than the previous method.

关键词： BIST-aided scan test test data reduction compatible flip-flops test pattern generation scan chain ordering

作者: Masashi Ishikawa Hiroyuki Yotsuyanagi Masaki Hashizume

作者单位: Dept. of Information Solution, Institute of Technology and Science the University of Tokushima 2-1 Minami-Josanjima, Tokushima 770-8506, JAPAN

会议类型: 国际会议

会议名称: 2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

会议地点: 上海

会议语种:英文

页码: 163-166

在线出版日期: 2010-12-01（万方平台首次上网日期，不代表论文的发表时间）