D-Scale: A scalable system-level dependable method for MPSoCs
The increasing failure rates observed in very deep sub micron silicon technologies pose a major problem to the design of future high-density SoCs. While hardening techniques originated from critical application areas (automotive, avionics) exist, they usually incur a cost overhead that renders them inadequate for consumer market segments. Thus we present a concept, an implementation and an evaluation of a scalable software-hardware detection, isolation and recovery method. The method exploits the natural redundancy that exists in MPSoCs for enhancing their reliability. Based on the assumption that a transient loss of functionality can be tolerated, the proposed scheme relies on a hardware/software framework that makes it possible to diagnose and to isolate faulty processors in a distributed manner. It guarantees the integrity, improves the availability and eases the maintainability of the MPSoC at system-level.
Dependable embedded multiprocessor availability enhancement low hardware overhead scalable software protection fault isolation
Nicolas Hebert Pascal Benoit Gilles Sassatelli Lionel Torres
STMicroelectronics Crolles, France LIRMM, CNRS and University of Montpellier 2 Montpellier, France LIRMM, CNRS and University of Montpellier 2 Montpellier, France
国际会议
2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)
上海
英文
198-205
2010-12-01（万方平台首次上网日期，不代表论文的发表时间）