Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits

摘要：

A globally-asynchronous and locally-synchronous (GALS) system has been known as a realistic hardware design solution for many difficulties such as global clock network that arise due to the continuous scaling of semiconductor technology. Although a full scan design method for synchronous circuits is applied to asynchronous circuits to achieve the same testability of their combinational parts, the overhead is extremely high. To reduce the overhead, several full scan design methods have been proposed but they cannot guarantee complete test In this paper, we propose a bipartite full scan design as a new DFT method for asynchronous circuit where we guarantee complete test for both combinational and sequential parts of circuits with area and performance overhead comparable to the previous best method in terms of overhead.

关键词： Asynchronous circuit testing L1L2* full scan design bipartite full scan testability scannable C-element

作者: Hiroshi Iwata Satoshi Ohtake Michiko Inoue Hideo Fujiwara

作者单位: Graduate School of Information Science, Nara Institute of Science and Technology 8916-5 Takayama, Ikoma, Nara 630-0192, Japan Japan Science and Technology Agency, CREST

会议类型: 国际会议

会议名称: 2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

会议地点: 上海

会议语种:英文

页码: 206-211

在线出版日期: 2010-12-01（万方平台首次上网日期，不代表论文的发表时间）