At-speed Test of High-speed DUT using Built-off Test Interface

摘要：

This paper presents an efficient test framework to extend a use of low-cost ATE (Automatic Test Equipment) to at-speed test of high-speed DUT (Device Under Test). To bridge the speed gap between the ATE and the DUT, an off-chip test interface circuit, called Built-off Test Interface (BOTI), has been developed. Unlike the previous methods which use onchip or off-chip self-test circuits, in our method, the ATE plays main role in testing high-speed DUTs by actively controlling the BOTI operation, and monitoring the overall test procedure. This makes the presented method flexible to be applied to various test applications without compromising the test coverage. Also, since the BOTI is implemented offchip, it does not require hardware modifications of the ATE or the DUT except the DUT loadboard to accommodate the BOTI module. To maintain reliable off-chip signal communication between the BOTI and the DUT, the BOTI measures off-chip channel skew and compensates the measured skew when communicating signals with the DUT. Currently, the BOTI is configured to do the at-speed test of high-speed memory. The measurement results are presented to validate the functionality of the BOTI, and the effectiveness of the presented test framework.

关键词： At-speed Test High-speed Memory Test Design for Testability ATE Hardware Off-chip Test Interface

作者: Joonsune Park Jae Wook Lee Jaeyong Chung Eonjo Byun Cheol-Jong Woo Sejang Oh

作者单位: Kihyuk Han and Jacob A. Abraham Computer Engineering Research Center The University of Texas at Aust Samsung Electronics, Giheung, Korea

会议类型: 国际会议

会议名称: 2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

会议地点: 上海

会议语种:英文

页码: 269-274

在线出版日期: 2010-12-01（万方平台首次上网日期，不代表论文的发表时间）