Circuit Topology-Based Test Pattern Generation for Small-Delay Defects

摘要：

For sub-nanometer designs, testing for small-delay defects (SDDs) is essential to achieve low defect escapes for the manufactured silicon. Existing solutions for testing SDDs are not practical for high-volume production environments due to large pattern count or long compute time, or both. In this paper, we present a production-friendly method that takes the circuit topology into account while generating patterns for SDDs. Experimental results on several IWLS05 benchmark and six industrial circuits show that compared to the default timing-aware pattern set; the proposed method reduces pattern count an average of 172％ for IWLS benchmarks and an average of 105％ for industrial circuits. We demonstrate the production-worthiness of our approach by using several quality metrics and showing that the proposed method provides similar or higher coverage for SDDs compared to the default timing-aware ATPG, but only with a significantly small number of test patterns and in significantly small run time.

作者: Sandeep Kumar Goel Krishnendu Chakrabarty Mahmut Yilmaz Ke Peng Mohammad Tehranipoor

作者单位: Dept. Electrical & Computer Engg. Duke University Durham, N.C. 27708, USA Advanced Micro Devices, Inc. 1 AMD Place Sunnyvale, Calif. 94085, USA Dept. Electrical & Computer Engg. University of Connecticut Storrs, Conn. 06269, USA

会议类型: 国际会议

会议名称: 2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

会议地点: 上海

会议语种:英文

页码: 307-312

在线出版日期: 2010-12-01（万方平台首次上网日期，不代表论文的发表时间）