Distinguishing Resistive Small Delay Defects from Random Parameter Variations
As technology scales, resistive defects, particularly via voids, are becoming an increasing problem. While such defects may only cause a small timing increase along some signal paths during test, they often grow and lead to early life failures in the field. Testing for small delay defects is therefore receiving considerable attention in recent years because the traditional burn-in approach to screen out such infant mortality failures is becoming prohibitively expensive in nanometer scale technologies. Unfortunately, random process variations can give rise to variability in circuit timing comparable to the resistive delay faults being targeted. This makes it critical to distinguish between the two so as to avoid discarding slow parts that are not reliability risks and can in fact be appropriately speed binned and safely used. In this paper we present a innovative strategy to show how this can be done by observing the relative change to switching delay of the slow path with variation in the power supply voltage. Our proposed approach exploits a novel key observation that the relative delay contribution of a performance outlier transistor increases noticeably with decreasing VDD, while the relative delay contribution from resistive delay defects decreases with increasing VDD.
Small delay defect variability early life failure
Xi Qian Adit D. Singh
ECE Department, Auburn University Auburn, AL, USA
国际会议
2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)
上海
英文
325-330
2010-12-01（万方平台首次上网日期，不代表论文的发表时间）