会议专题

A Noise-Aware Hybrid Method for SDD Pattern Grading and Selection

Testing for small-delay defects (SDDs) is necessary for ensuring product quality in smaller technology nodes. Current tools such as transition-delay fault (TI)F) ATPGs and timing-aware ATPGs are either inefficient in detecting SDDs or suffering from large pattern count and CPU runtime. Furthermore, none of these methodologies take into account the impact of pattern-induced noises, e.g., power supply noise (PSN) and crosstalk, which are potential sources of SDDs. In this paper, we present a hybrid method considering the impacts of pattern-induced noises to grade and select the most effective patterns for detecting SDDs. The grading procedure is performed on a large repository of patterns generated by n-detect TDF ATPG. Top-off ATPG is performed after pattern selection to achieve the same fault coverage as that for timing-aware ATPG. The experimental results demonstrate the efficiency of our proposed method; it results in a pattern count close to 1-detect ATPG while sensitizes similar or greater number of long paths than the commercial tuning-aware ATPG pattern set.

Delay test small-delay defects pattern selection power supply noise crosstalk

Ke Peng Mahmut Yilmaz Krishnendu Chakrabarty Mohammad Tehranipoor

ECE Department, University of Connecticut Advanced Micro Devices, Inc., Sunnyvale, California ECE Department, Duke University

国际会议

2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

上海

英文

331-336

2010-12-01(万方平台首次上网日期,不代表论文的发表时间)