A Low Area On-Chip Delay Measurement System Using Embedded Delay Measurement Circuit
This paper presents a low area on-chip delay measurement system using an embedded delay measurement circuit. To reduce the area, the proposed method does not demand the measurement of the exact path under measurement, but the measurement of a path including the path under measurement and wires of clock tree unlike the conventional methods. The proposed Stop Signal Generator (SSG) consists of OR gate trees and a selector circuit. In addition, the area of SSG is lower than the conventional one. SSG is additional circuit which sends the transition from the output of the path under measurement to the embedded delay measurement circuit. Therefore, the area of the proposed system is lower. Because the area is low, the proposed method can be used for small-delay defect detection in manufacturing testing and failure prediction due to aging after shipment. We can apply the proposed delay measurement system to any embedded delay measurement circuit that measures the time difference between the two input signal transitions sent to the circuit. The evaluation shows that the area overhead is 16.54％. It is 6.62％ smaller than the conventional method, and 8.41％ larger than standard scan design.
on-cMp delay measurement embedded delay measurement circuit direct delay measurement small-delay defect detection failure prediction
Kentaroh Katoh Kazuteru Namba Hideo Ito
Dept. of Informatics & Imaging Sciences Chiba University Chiba, Japan Graduate School of Advanced Integration Sciences Chiba University Chiba, Japan
国际会议
2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)
上海
英文
343-348
2010-12-01（万方平台首次上网日期，不代表论文的发表时间）