Test Cost Analysis for 3D Die-to-Wafer Stacking

摘要：

The industry is preparing itself for threedimensional stacked ICs (3D-SlCs); a technology that promises heterogeneous integration with higher performance and lower power dissipation at a smaller footprint. Several 3D stacking approaches are under development. From a yield point of view, Die-to-Wafer (D2W) stacking seems the most favorable approach, due to the ability of Known Good Die stacking. Minimizing the test cost for such a stacking approach is a challenging task. Every manufactured chip has to be tested, and any tiny test saving per 3D-SIC impacts the overall cost, especially in high-volume production. This paper establishes a cost model for D2W SICs and investigates the impact of the test cost for different test flows. It first introduces a framework covering different test flows for 3D D2W ICs. Subsequently, it proposes a test cost model to estimate the impact of the test flow on the overall 3D-SIC cost. Our simulation results show that (a) test flows with pre-bond testing significantly reduce the overall cost, (b) a cheaper test flow does not necessary result in lower overall cost, (c) test flows with intermediate tests (performed during the stacking process) pay off, (d) the most costeffective test flow consists of pre-bond tests and strongly depends on the stack yield; hence, adapting the test according the stack yield is the best approach to use.

关键词： 3D test flow 3D test cost Die-to-Wafer stacking 3D manufacturing cost Through-Silicon-Via

作者: Mottaqiallah Taouil Said Hamdioui Kees Beenakker Erik Jan Marinissen

作者单位: Computer Engineering Lab Delft University of Technology Faculty of EE, Mathematics and CS Mekelweg 4 DIMES Technology Center Delft University of Technology Faculty of EE, Mathematics and CS Mekelweg 4, IMEC vzw 3D Integration Program Kapeldreef 75, 3001 Leuven, Belgium

会议类型: 国际会议

会议名称: 2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

会议地点: 上海

会议语种:英文

页码: 435-441

在线出版日期: 2010-12-01（万方平台首次上网日期，不代表论文的发表时间）