Test Time Analysis for IEEE P1687

摘要：

The IEEE P1687 (UTAG) standard proposal aims at providing a standardized interface between on-chip embedded logic (instruments), such as scan-chains and temperature sensors, and the IEEE 1149.1 standard which provides test data transport and test protocol for board test A key feature in P1687 is to include Select Instrument Bits (SIBs) in the scan path to allow flexibility in test architecture design and test scheduling. This paper presents algorithms to compute the test tune in a P16S7 context The algorithms are based on analysis for flat and hierarchical test architectures, considering two test schedule types - concurrent and sequential test scheduling. Furthermore, two types of overhead are identified, i.e. control data overhead and JTAG protocol overhead. The algorithms are implemented and employed in experiments on realistic industrial designs.

关键词： Test Time Calculation IEEE P1687 UTAG lest Architectures Test Schedules

作者: Farrokh Ghani Zadegan Urban Ingelsson Gunnar Carlsson Erik Larsson

作者单位: Linkoping University, Linkoping, Sweden Ericsson AB, Stockholm, Sweden

会议类型: 国际会议

会议名称: 2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

会议地点: 上海

会议语种:英文

页码: 455-460

在线出版日期: 2010-12-01（万方平台首次上网日期，不代表论文的发表时间）