Design of SATA2.0 Data-Encryption/Decryption Device Controller

摘要：

In order to improve the security of data storages technology, a SATA2.0 Data Encryption/Decryption Device Controller is presented in this paper. This controller realizes the data encryption/decryption with the 128hits AES algorithm based on symmetrical patterns CBC while implementing the functions of the SATA2.S standard. The design architecture is written in Verilog HDL, and verified the feasibility with the Xilinx ChipScope pro based on Xilinx Virtex-5 XC5VLX50T FPGA.

关键词： data encryption/decryption SATA2.0 device controller AES algorithm symmetrical patterns CBC

作者: Sang Xu Yan Bo Li Guangjun

作者单位: School of Communication and Information Engineering University of Electronic Science and Technology of China Chengdu, China

会议类型: 国际会议

会议名称: 2010 International Conference on Measurement and Control Engineering(2010年IEEE测量与控制工程国际会议 ICMCE2010)

会议地点: 成都

会议语种:英文

页码: 705-708

在线出版日期: 2010-11-16（万方平台首次上网日期，不代表论文的发表时间）