Mobility Enhancement in Silicon Nanowire Transistors

摘要：

Electron and hole mobility in sub-10nm silicon nanowire FETs on (100) SOI has been systematically investigated experimentally. The nanowire height of fabricated nanowire FETs is as low as 4 - 10nm and the minimum nanowire width is shrunk to 5nm. Higher hole mobility than (100) universal mobility is experimentally observed for the first time in 9nmwide nanowire and even in 5nm-wide nanowire, while electron mobility degradation is minimized in nanowire nFET. Underlying physical mechanisms are discussed.

作者: Toshiro Hiramoto Jiezhi Chen Takuya Saraya

作者单位: Institute of Industrial Scicnce, University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 9-12

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）