Low-Voltage Memory-Rich Nanoscale CMOS LSIs-Current Status and Future Trends
The minimum operating voltage, Vmin, of memory-rich nanoscale CMOS LSIs is investigated to open the door to the below 0.5-V era. A new method using a timing margin is proposed to evaluate Vmin. It shows that Vmin is very sensitive to the threshold-voltage variations, AV,, which become more significant with device scaling, and to the lowest necessary threshold voltage, Vto, of MOSFETs. As a result of comparing the Vmins of logic, SRAM, and DRAM blocks, it turns out that the SRAM block is problematic because it has the highest Vmin despite using RAM repair techniques. Various techniques are thus reviewed, including shortening the data line, up-sizing the MOSFETs, and control of the common source line or the word line. To further reduce the Vmins of the blocks, △Vr,immune MOSFETs such as a planar fully-depleted structure (FD-SOI) and fin-type structure (FinFET), and ow-V10 circuits are discussed, showing the below 0.5-V CMOS era to be feasible to come.
Kiyoo Itoh
Central Research Laboratory, Hitachi, Ltd.,Kokubunji, Tokyo 185-8601, Japan
国际会议
上海
英文
25-28
2010-11-01（万方平台首次上网日期，不代表论文的发表时间）