Nanofabrication Processes Integration of CMOS Transistor Gate/Sidewall Spacer Patterning

摘要：

In recent CMOS technologies, sidewall spacers play an important role in the control of short channel effects by offsetting ion implantation profiles from the edge of the gate. The present approach to overcome these fabrication limitations. The spacer patterning technology yields critical dimension variations of minimum-sized features which are much smaller than achieved by optical integrated lithography and etching processes. Generally relates to semiconductor manufacturing, and more particularly to nanotechnology fabrication feasibility for CMOS wafer process on gate spacer technology manufacture feasibility. A modified sidewall spacer patterning method was implemented for using conventional lithography and etching processing technology. Based on the systematical investigation of the effects of the various etch conditions on etching profile and their impacts on the sidewall transistor gate structure, a novel integrated process for well controlled sidewall spacer formation was developed for fabrication.

作者: Chun-Jen Weng

作者单位: Dept. of Technology Management, Leader University, Tainan, Taiwan, R.O.C

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 84-86

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）