Low-Power Accessless SRAM Macro in Logic CMOS Technology

摘要：

In this paper, a novel low-power SRAM based on 4transistor (4T) latch cell is described. The memory cells are composed of two cross-coupled inverters without access transistors. The sources of PMOS transistors are connected to bitlines while the sources of NMOS transistors are connected to wordlines. They are accessed by totally new read and write method which results in low operating power dissipation in the nature. A 1.8 V SRAM test chip has been fabricated in a 0.18 μm CMOS technology, which demonstrated the functionality of the memory cell. This new SRAM operates with 30％ reduction in read power and 42％ reduction in write power compared to the conventional 6-transistor (6T) SRAM.

作者: Jae-Ho Ryu Weijie Cheng Yong-Woon Kim Jeong-Wook Cho Yeonbae Chung

作者单位: School of Electrical Engineering and Computer Science, Kyungpook National University, Daegu, Rep. of Korea

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 90-92

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）