A Novel High-Performance Junctionless Vertical MOSFET Produced on Bulk-Si Wafer

摘要：

In this paper, we propose a junctionless vertical MOSFET (JLVMOS) based on bulk-Si wafer. According to the numerical simulations, the proposed JLVMOS can get a steep subthreshold swing (S. Swing), reduced DIBL, and higher Ion/Ioff ratio, in comparison to a junctionless planar SOI MOSFET. This is bccause the vertical double-gate (DG) structure truly helps reduce the short-channel effects (SCEs). More importantly, SOI wafer is not necessary as a starting material for our proposed junctionless transistor, which is good for low-cost mass production.

作者: Chih-Hsuan Tai Jyi-Tsong Lin Yi-Chuen Eng Po-Hsieh Lin

作者单位: Dept. of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan R.O.C

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 108-110

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）