A new method to reduce VDMOS on-resistance in BCD process

摘要：

This paper focused on special requirement of low onresistance of VDMOS in BCD process. VDMOS structure and its process were studied, and a method for decreasing on-resistance of VDMOS was developed. In this method, a 10 urn deep trapezia ring was formed on the N+ ring of D electrode of VDMOS, and a few more steps were added to ordinary BCD process. Using the method, N-type VDMOS transistor with low onresistance was obtained, which is approximately 30％ lower than that of similar device in BCD process. For the new N-type VDMOS, BVDS and VT is 80V and 2.5V, respectively.

作者: Zhengyuan Zhang Zhicheng Feng yong mei jiangen Li Xiaogang Li

作者单位: National Laboratory of Analog Integrated Circuits, Chongqing, China 400060 Sichuan institute of solid-state circuits, Chongqing, China 400060

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 117-119

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）