A low power 14-bit 1 MS/s Differential SAR ADC with On Chip Multi-Segment Bandgap Reference

摘要：

As a key element in mixed-signal ICs, the SAR architecture has advantages of low power consumption, medium speed and high resolution. However, for the common architecture, there are still some limitation such as low time efficiency, sensitive to the noise of digital part and need high precision outside reference voltage to ensure performance 1. In this paper, a 14-bit low power self-timed differential SAR ADC with a new structure high precision multi-segment bandgap reference (BGR) is presented. In this design, Self-timed bit-cycling is adopted to enhance the time efficiency. Gray coding.

作者: Qiao Ning Liu Silin Yu Fang Liu Zhongli

作者单位: Institute of Semiconductors, Chinese academy of science, Beijing 100083, China Department of Electro Institute of Semiconductors, Chinese academy of science, Beijing 100083, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 205-207

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）