A 12-Bit 125MSPS ADC With Capacitor Mismatch Trimming

摘要：

In this paper, a 7 stage switched capacitor pipelined ADC is described. This ADC is designed to achieve 12bit resolution at the speed up to 125MSPS, which uses a fully differential switched capacitor pipelined architecture. This ADC includes an input broadband buffer, a high performance sample-and-hold+ amplifier (SHA) front end, and 7 pipelined sub-ADC stages. A double poly triple metal 0.35um BiCMOS process with 5V analog power supply is used in the design. This ADC achieves an SNR of 66dB and an SFDR of 80dB for sampling analog input frequencies up to 50MHz.

关键词： switched capacitor SHA Trimming DEM

作者: Liang Li Xingfa Huang Zhou Yu Mingyuan Xu Can Zhu Yong Han

作者单位: National Key Labs of Analog ICs, Chongqing 400060, P.R.China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 216-218

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）