The Design and Implementation of Two-Cycle NoC Router

摘要：

With the number of processor cores increasing in chip multi-processors (CMPs) and global wire delays increasing, networks on chip have been gaining wide acceptance for on-chip inter-core communication. This paper introduces a low latency Dynamic Virtual Output Queues Router (DVOQR), which can reduce the router latency to two cycles by leveraging look-ahead routing computation and virtual output address queues scheme. The results with place and route used by Cadence Encounter in TSMC 65nm technology display that the frequency of DVOQR can reach 1.4 GHz , the cell area of the router is only 0.424mm2 and the power consumption is 274 mw under the 50％ injection rate.

作者: Qi Shubo Li Jinwen Zhao Tianlei Jia Xiaomin Zhang Minxuan

作者单位: School of Computer Science. National University of Defense Technology. Changsha 410073. Hunan, China

会议类型: 国际会议

会议名称: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

会议地点: 上海

会议语种:英文

页码: 233-235

在线出版日期: 2010-11-01（万方平台首次上网日期，不代表论文的发表时间）